The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a CMOS decoding circuit for generating complementary decode signals.
A processor comprising a read-only memory (ROM), an electrically erasable and programmable ROM (EEPROM) and a central processing unit (CPU) has a CMOS decoding circuit for decoding input signals so as to output complementary decode signals which are out of phase with each other. FIG. 1 is a circuit diagram showing a CMOS decoding circuit of a semiconductor memory device for generating decode signals XPia, XPib.
The CMOS decoding circuit has a two input NAND gate 101 which is supplied with address signals Ca, Da and whose output node N1 is electrically connected to an inverter 103 and connected to an inverter 105 via the inverter 103 and a node N2.
When the address signals Ca, Da are input to the NAND gate 101, the NAND gate 101 determines a negative AND and outputs an output signal indicative of the result of negative ANDing at the node N1. The output signal is inverted by the inverter 103 to produce a first inverted signal. Then, the first inverted signal is delivered to the node N2 to be output as a decode signal XPia. The first inverted signal is inverted again by the inverter 105 to be output as an inverted decode signal XPib from the node N3. Since the output signal referred to above is successively inverted by the inverters 103, 105, the output signal is delivered to the node N3 after a signal propagation delay.
When the address signals Ca, Da are both "H" in level (i.e., Upon selection of both address signals Ca, Da as the "H" level), the CMOS decoding circuit outputs a decode signal XPia of an "H" level and an inverted decode signal XPib of an "L" level. When, on the other hand, either one of the address signals Ca, Da is "L" in level (i.e., Upon non-selection of either of the address signals Ca, Da as the "H" level), the CMOS decoding circuit outputs a decode signal XPia of an "L" level and an inverted decode signal XPib of an "H" level.
In the CMOS decoding circuit shown in FIG. 1, as described above, the decode signal XPia is inverted to produce the inverted decode signal XPib, thereby outputting the complementary decode signals XPia, XPib from the CMOS decoding circuit. Therefore, the phase of the decode signal XPia is shifted from that of the decode signal XPib by the propagation delay time of the inverter 105 because the decode signal XPia is fed through only one inverter whereas the decode signal XPib is fed through two inverters.
When a circuit for a semiconductor memory device is designed on a large scale and the capacity of each inverter for driving a load is increased in particular, the phase difference or shift between, the decode signals XPia and XPib becomes correspondingly greater. Consequently, the D.C. current momentarily flows into word line drivers supplied with the outputs of the CMOS decoding circuit during a period in which the phase .. difference between the decode signals XPia and XPib is being produced, thereby increasing the power consumption of the semiconductor memory device. In addition, the signal propagation or transfer speed is determined by either the decode signal XPia or XPib which has a phase lag, thereby creating a difficulty in operating the CMOS decoding circuit at a high speed.